The DeepSeek Leak and China’s AI Hardware Claims

From the DeepSeek leak to Meituan’s 50,000-chip cluster, we test the biggest recent claims about China’s AI hardware stack with Ryan Cunningham of Machine Yearning.

Things you might have missed

A few items from the past week worth having on your radar.

From our recent coverage:

• Moonshot AI’s latest round grew to $3.5 billion. The oversubscribed financing values the Kimi developer at $35 billion post-money, while the company is already discussing a pre-IPO round at a $50 billion valuation. Read more →

• CXMT surged nearly 500% on its first day of trading. The debut valued China’s leading DRAM producer at roughly RMB500 billion, making it the country’s largest domestically listed company by market capitalization. We wrote about the stakes ahead of the IPO; since then, ByteDance has signed a $7 billion supply agreement with CXMT, adding to its existing long-term deal with Tencent. Read the latest →

• DeepSeek’s latest V4 release suggests the model race is shifting toward agent performance. As we publish, DeepSeek has released the official V4-Flash API in public beta and opened the weights for V4-Flash-0731. The underlying architecture and model size are unchanged from April’s preview; the gains come from additional post-training. DeepSeek says the updated model now substantially outperforms V4-Pro Preview across several agent and coding benchmarks. The official V4-Pro release is expected next. See the model →

And in the media …

• Nikkei Asia (July 25, 2026): We were featured in its report on China’s $18 billion microdrama industry and the growing use of AI to replace parts of live-action production. Read more →

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As Tech Buzz China expands coverage of China’s semiconductor industry, we’re building a comprehensive interactive map of the Chinese semiconductor ecosystem.

This analysis is part of that broader effort. Ryan Cunningham, the co-author of this piece, will also publish a substantially more detailed companion analysis on his Substack Machine Yearning, including the full technical methodology, calculations, and supporting evidence.

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DeepSeek’s first institutional fundraising round in July 2026 unexpectedly produced one of the most closely scrutinized documents in China’s AI industry.

As part of the process, founder Liang Wenfeng spent approximately four hours answering investors’ questions in what was intended to be a private discussion. A transcript subsequently circulated widely online. On July 25, Bloomberg reported that DeepSeek had paused its planned follow-on fundraising round, with Liang reportedly frustrated that confidential investor discussions had become public.

The leak matters not simply because of what Liang said, but because of how specific he was. The transcript ranges across Huawei’s AI systems, DeepSeek’s computing infrastructure, model training and deployment, and the future of China’s domestic AI stack. This report does not attempt to summarize the full transcript. Instead, it examines several of its most consequential technical claims. How capable are Huawei’s AI systems in practice? What could DeepSeek realistically accomplish with its reported compute resources? Is Meituan’s claim that it trained a one-trillion-parameter model on a 50,000-accelerator domestic cluster technically plausible? How should Liang’s comparison between Huawei hardware and Nvidia’s GB300 be interpreted? And, most importantly, how close is China to training frontier models entirely on domestic hardware?

Drawing on public disclosures, technical papers, supply-chain data, industry reporting, and bottom-up engineering estimates, Ryan Cunningham leads an evaluation of each claim on its own merits.

Did DeepSeek Train Its Model on Huawei?

When DeepSeek released its V4 Preview on April 24, 2026, the company said the model had been optimized for Huawei’s Ascend platform. Huawei announced that its Ascend 950 systems would support V4, and Reuters later reported that Ascend chips had been used in some of the model’s training.

The word “training,” however, covers several stages. Pre-training is the expensive initial process in which a model learns from trillions of tokens. It is followed by less compute-intensive work such as fine-tuning, reinforcement learning and synthetic-data generation. Huawei’s statement did not specify which stage used Ascend hardware.

The leaked investor transcript provides another clue. Liang Wenfeng reportedly said DeepSeek had been allocated roughly 16,000 Huawei accelerators, which he described as equivalent to about 4,000 NVIDIA B-series GPUs. The arithmetic broadly supports that comparison, although the exact ratio depends on the Huawei chips involved.

DeepSeek’s models are trained in FP8 precision, a format which reduces memory and computing requirements by storing weights with half the number of bits in full-precision models. Huawei’s Ascend 910C does not natively support FP8 as a bit precision. DeepSeek has historically run its models on 910Cs by converting them into INT8 precision, so this is possible. But Liang mentions the 950-series specifically in investor Q&A, and these do support FP8.

In full precision, which many commentators default to in chip comparisons, 16K 910Cs would be roughly equivalent to 5.0 - 5.5K NVIDIA Blackwell-series GPUs. For the newer 950-series, the exchange rate is closer to 4.5 - 5.1:1 Ascend to Blackwell. Liang’s four-to-one estimate falls broadly within this range.

Training and inference place different demands on those chips. Training requires enormous amounts of computation to calculate how the model’s parameters should change. Inference—the process of answering users—is often constrained by memory bandwidth, or how quickly chips can move the model and its conversation history through memory. NVIDIA’s advantage is greatest in compute-heavy training, while Huawei is more competitive in memory-bound inference.

System design also matters. Sixteen thousand chips could form approximately 42 CloudMatrix 384 supernodes, consuming about 23 megawatts across the fleet. Each supernode connects 384 Ascend processors so they can operate as one large machine, approximately the right unit for serving a model as large as DeepSeek V4 without repeatedly moving data among smaller eight-chip servers.

Our first-principles model (technical details to be released in Ryan’s companion piece) estimates that an all-V4 Flash fleet could process about 24 trillion total tokens per day, while an all-V4 Pro fleet would process about 6.9 trillion. These figures include both the text generated by the model and the prompts, documents and conversation history it must read.

Actual deployments perform below theoretical estimates because of networking delays, hardware failures and uneven workloads. Adjusting for the gap between our model and measured systems puts a Flash-heavy fleet at roughly 11–17 trillion total tokens per day. V4 Flash already handles an estimated 70% of DeepSeek’s agentic traffic, and the same fleet could run evaluations and generate synthetic data alongside production requests.

InferenceX offers a useful comparison, although its test gave NVIDIA several advantages: faster settings, shorter prompts and software optimized specifically for NVIDIA chips. A 72-chip GB300 rack demonstrated capacity of about 79 billion tokens per day—not 79 trillion.

Our model estimates that 16,000 Ascend chips could have theoretical capacity of 6.9 trillion tokens per day, with 3.1–4.8 trillion more realistic after allowing for downtime and uneven demand. These are estimates of how much text the hardware could process at high utilization, not claims that DeepSeek is actually serving that volume. The comparison still suggests that one B300 can provide roughly the inference capacity of three to five Ascend chips, making Liang’s four-to-one estimate broadly reasonable. We investigate the 4:1 claim more thoroughly further down.

What About Post-Training?

Much of post-training has hardware requirements similar to inference. Reinforcement-learning rollouts ask the model to generate large numbers of possible answers. Reward models score those answers, evaluation systems test them, and synthetic-data pipelines produce new examples for later training. These workloads mostly involve running trained models repeatedly across independent copies.

Modern reinforcement learning spends most of its time generating possible answers rather than updating the model’s parameters. Supervised fine-tuning and continued full-model training are more demanding. Every step requires the chips to calculate changes to the model’s parameters and synchronize them across the cluster. Communication delays, chip failures or unstable connections can then slow or interrupt the entire run—problems we examine later through LongCat.

Based on DeepSeek’s estimated revenue and published API prices, imply current demand of roughly 3–10 trillion tokens per day across its API and enterprise products. OpenRouter alone routes approximately 1.1 trillion tokens per day to DeepSeek’s three leading models. Note these figures do not include token throughput from its free chat interface.

The available evidence therefore supports a limited conclusion: a 16,000-chip Ascend fleet could plausibly carry DeepSeek’s current inference demand and much of its post-training workload. It does not establish that V4’s initial pre-training was performed on Huawei hardware.

Can Meituan LongCat (1.6 Trillion Parameters) Really Be Trained on 50,000 Domestic Chips?

We first wrote about Meituan’s LongCat 2.0 in June, after Meituan disclosed that the 1.6-trillion-parameter model had been trained on more than 50,000 domestic accelerators. We thought the announcement was important both for LongCat’s role inside Meituan’s local-commerce system and for what the training run suggested about China’s progress on domestic hardware.

This time, Ryan examines the 50,000-chip claim technically: how much computation the model required, which domestic accelerators were probably used, how the cluster may have been organized and what Meituan’s disclosures do and do not establish about China’s ability to train large models without NVIDIA hardware.

The first number to unpack is the headline parameter count. LongCat is a mixture-of-experts model, so it does not use all 1.6 trillion parameters for every token. It activates an average of roughly 48 billion parameters at a time, varying between 33 billion and 56 billion depending on the complexity of the input. About 97% of the model remains inactive during any individual calculation, making the training requirement much smaller than the headline figure suggests.

Using Meituan’s disclosed corpus of more than 35 trillion tokens, we estimate that LongCat required approximately 1.0×10²⁵ FLOPs—the total computational work performed across the training run, rather than the speed of any individual chip. Had all 1.6 trillion parameters been active for every token, the same corpus would have required approximately 3.4×10²⁶ FLOPs, or 33 times more compute.

(For technically inclined readers: we use the standard approximation of six times active parameters multiplied by training tokens. For mixture-of-experts models, active parameters provide a better estimate of computational work than total parameters, although the formula excludes attention, routing, embeddings and communication overhead. The result should therefore be read as an order-of-magnitude estimate, not Meituan’s measured training total.)

LongCat’s architecture also appears designed around the limitations of domestic hardware. Its sparse-attention system reduces how much of the context the model must examine at each step. A 135-billion-parameter embedding block stores recurring token patterns directly, shifting part of the workload from calculation toward memory. Multi-token prediction allows the model to predict several future tokens at once.

Meituan also divided the training work across the cluster in six different ways, including splitting the model’s experts, data, sequence and processing stages among different chips. It created an additional method specifically for distributing the large embedding block. The aim was to compensate for weaker individual accelerators by using more of them in parallel.

The physical cluster followed the same logic. Meituan organized the chips into superpods containing up to 48 machines, with fast connections inside each superpod and specialized interconnect between the superpods. The company says this topology increased pre-training throughput by roughly 30%.

One disclosure substantially narrows the likely hardware. Meituan said its accelerators had less memory than an NVIDIA H800, which has 80 GB, and that memory became the primary bottleneck. That rules out Huawei’s Ascend 910C, which has 128 GB, and the 950 series, which has between 112 GB and 144 GB. The 950DT’s late-2026 availability makes it even less plausible.

The description instead points toward Ascend 910B-class hardware with 64 GB of memory, or a comparable domestic accelerator. Assuming this, our base case estimates approximately 1.7 million accelerator-days of training, which is consistent with Meituan’s model report. Across 50,000 chips, the final training run would take about 33 days.

The estimate depends on two assumptions. The first is model FLOPs utilization, or MFU: the share of each chip’s theoretical computing power that actually performs model calculations. We use 30%, based on Huawei’s reported result for a tuned Pangu Ultra training run across roughly 6,000 Ascend processors. The second is the share of elapsed time spent making training progress after allowing for failures, restarts and communication delays. We model a range of 40% to 75%.

The 910C and 950DT columns are counterfactual comparisons. Their memory capacities conflict with Meituan’s description of the hardware used.

Meituan says the full run completed without a rollback or an unrecoverable spike in the model’s error rate. It describes safeguards including deterministic operations, which make repeated calculations produce consistent results, and systems that detect random bit errors in memory. If accurate, that would indicate mature training operations across a very large domestic cluster, although the claim cannot be independently verified.

Huawei has separately reported reducing daily training failures by 70% and improving hardware utilization by 1.5 times. Neither claim includes a quantified starting point, so they provide little basis for comparison with NVIDIA-based systems.

Meituan’s account is technically feasible and internally consistent. The computing requirement, fleet size, memory constraint and network design all point toward a large training run on 910B-class hardware. The missing information is how efficiently it was completed: Meituan does not disclose the actual duration, achieved hardware utilization, failure rate or time lost to checkpointing and recovery.

Third-party benchmarks place LongCat around models such as Gemini 3.5 Flash-Lite and Nemotron 3 Ultra. It is a competent model with a frontier-scale parameter count, but its performance remains below the leading frontier systems. The evidence supports the claim that China can complete a training run of this scale on domestic hardware; it does not show that the resulting system matches the efficiency or model performance of the largest American clusters.

Does Four Ascend 950s Equal One NVIDIA GB300?

Liang’s claim that four Huawei chips equal one NVIDIA chip depends on the workload and the Ascend generation being compared. For memory and inference, four-to-one is reasonable. For frontier training, NVIDIA’s advantage is considerably larger.

The Ascend 950DT is closest to the GB300 in memory. A GB300 has roughly twice the memory capacity and bandwidth of a 950DT. The gap widens to about five-to-one when comparing raw computation using equivalent numerical formats.

The table separates theoretical specifications from delivered performance. “Dense” compute assumes all calculations are performed, rather than using NVIDIA’s headline figures for sparse workloads in which some operations can be skipped. Delivered inference measures how many tokens the systems can generate while maintaining an acceptable response speed for each user. The inference range covers V4 Flash, V4 Pro and LongCat 2.0.

Inference narrows the gap because generating each token often depends more on moving model data through memory than on raw arithmetic. Our system-level model puts a GB300 at roughly 2.9–3.3 times the inference throughput of an Ascend 950DT. Four-to-one is therefore a reasonable planning ratio and may even be slightly conservative for an Ascend-optimized deployment.

Energy produces a more surprising result. Although several Ascend chips are required to match one GB300’s throughput, the 950DT’s estimated energy use per generated token is approximately equal to the GB300’s. Huawei still needs more chips, networking equipment and rack space, but the inference energy cost is broadly competitive. Older Ascend 910Cs may have slightly better FP16 throughput, but are strictly worse in energy-compute. Its energy use per token is roughly 3x worse than that of the 950DT.

Training produces the opposite result. It depends more heavily on raw computation and requires the entire cluster to exchange updates continuously. Huawei has demonstrated roughly 30% model hardware utilization on large Ascend training runs, but communication delays, failures and recovery time reduce usable performance further. Our model puts the GB300’s delivered training throughput at approximately eight to ten times that of an Ascend 910C or 950DT.

The comparison therefore falls into three ranges:

• Memory capacity and bandwidth: approximately two-to-one

• Raw compute and delivered inference: approximately three-to-five-to-one

• Delivered frontier-training performance: approximately eight-to-ten-to-one

Liang’s four-to-one figure is a reasonable internal planning ratio for Ascend-optimized inference. It is not a general equivalence between Huawei and NVIDIA hardware, and it does not hold for frontier pre-training.

Could China Train Next Year’s Frontier Models Entirely on Domestic Chips?

There is no fixed number of chips required to train a frontier model. The calculation depends on the model architecture, training data, performance of the hardware and how long the developer is willing to wait. A smaller cluster can complete the same amount of work if it remains productive for longer.

A fixed computing threshold can also be misleading. The 2023 U.S. AI Executive Order used 10²⁶ FLOPs—the total number of calculations performed during training—as a reporting trigger. The figure has since become a common shorthand for “frontier” training. Epoch AI instead defines frontier models as the ten models trained with the most compute at the time of release, since the amount required changes as architectures and training methods improve.

Kimi K3 illustrates the problem with a fixed threshold. Western commentators have described it as a frontier-class model, yet its architecture substantially reduces the amount of computation required. K3 has 2.8 trillion total parameters but activates only 104 billion for each token, routing the work through 16 of its 896 experts. Moonshot has not disclosed its training corpus, so we use LongCat’s 35 trillion tokens as a working assumption. That produces an estimated pre-training requirement of approximately 2.4×10²⁵ FLOPs—slightly more than twice LongCat’s compute, but only about one-quarter of the Executive Order threshold.

This does not mean K3 was inexpensive to develop or that its reported capabilities are overstated. It means that a model’s training compute increasingly depends on architectural choices, and that a threshold written around earlier model designs may say less about capability over time.

Under our hardware assumptions, a 50,000-chip Ascend 950DT cluster could complete a K3-scale pre-training run in roughly 49 days, with a wider range of 33–146 days depending on hardware utilization and time lost to failures. A 90-day schedule would require approximately 27,000 chips, while finishing in 30 days would require about 81,000. For comparison, 50,000 NVIDIA GB300s could theoretically complete the same run in around five days.

Those estimates cover only the final run. Developing the model also requires testing architectures and datasets, training smaller experimental versions, extending context length and conducting post-training. The final run may represent one-fifth or less of the program’s total compute consumption. A laboratory therefore needs priority access to a large cluster for many months, rather than simply assembling enough chips for the final run.

Whether the cluster can remain productive for that long is less certain. Training a mixture-of-experts model requires constant communication as tokens are routed to different experts across the cluster. One slow or failed machine can delay thousands of others. Checkpointing and restarting consume additional time, while compiler problems, unstable communications and errors in low-precision calculations can interrupt training.

Meituan says LongCat completed training without rollbacks or irrecoverable loss spikes, showing that some of these operational problems can be managed on domestic hardware. But LongCat required less compute than the K3 example and performs below the leading frontier models. DeepSeek and Moonshot also still appear to reserve NVIDIA hardware for their most important training runs.

Our estimates suggest that 50,000–100,000 Ascend 950-class chips, available for much of a year, could support a predominantly domestic K3-scale training program. The model would probably need to be designed around Huawei’s memory, networking and software constraints.

The Wider Industry Context

China’s domestic compute supply extends beyond Huawei. Cambricon shipped an estimated 142,000 accelerators in 2025, Iluvatar CoreX had reportedly delivered approximately 52,000 by mid-year, and Biren has disclosed more than 10,000 deployed GPUs. Kunlunxin, Moore Threads, Enflame and chips developed internally by Chinese internet companies add further capacity.

These processors cannot simply be combined into one tightly synchronized training cluster. They use different software, communication systems and numerical formats. Platforms such as SenseTime’s SenseCore, the Shanghai AI Laboratory’s DeepLink, and Phancy’s HAMi vGPU and ModelHub X can assign separate workloads to different hardware and reduce the engineering required to move models between chip families. Public evidence for training a single model across several vendors remains limited.

The broader supply base can still run experiments, evaluations, fine-tuning and inference, preserving large, uniform Ascend clusters for the main training run. The amount China can deploy will also depend on fabrication yields, high-bandwidth memory, advanced packaging, optical networking and data-center construction.

In conclusion, China’s domestic AI stack is approaching practical self-sufficiency, though at a substantial efficiency cost. Huawei hardware already appears capable of supporting large-scale inference and much of post-training, while LongCat shows that domestic clusters can complete very large pre-training runs. The remaining gap is measured in the extra chips, time, power and engineering required to match NVIDIA-based systems. This also complicates the impact of export controls: restricting access to the best hardware can slow Chinese developers and raise their costs, but increasingly may shape how they design models and clusters rather than determine whether those models can be built.